Encoding:

Format:

EXTRV[_RS].W 

EXTRV.W   rt, ac, rs

EXTRV_R.W rt, ac, rs

EXTRV_RS.W rt, ac, rs

Purpose:

Extract Word Value With Variable Right Shift From Accumulator to GPR

Extract a word value from a 64-bit accumulator to a GPR with variable right shift, and with optional rounding or rounding and saturation.

Description:

rt = sign_extend(sat32(round(ac >> rs5..0)))

The value in accumulator ac is shifted right by shift bits with sign extension (arithmetic shift right). The lower 32 bits of the shifted value are then sign extended to 64-bits and written to the destination register rt. The number of bits to shift is given by the five least-significant bits of register rs; the remaining bits of rs are ignored.

The rounding variant of the instruction adds a 1 at the most-significant discarded bit position. The 32 least-significant bits of the rounded result are then sign extended to 64-bits and written to the destination register.

The rounding and saturating variant of the instruction adds a 1 at the most-significant discarded bit position. If the rounding operation results in an overflow, the shifted value is clamped to the maximum positive Q31 fractional value

(0x7FFFFFFF hexadecimal). The rounded and saturated result is then sign extended to 64-bits and written to the destination register.

The value of ac can range from 0 to 3. When ac=0, this refers to the original HI/LO register pair of the MIPS64 architecture. After the execution of this instruction, ac remains unmodified.

For all variants of the instruction, including EXTRV.W, bit 23 of the DSPControl register is set to 1 if either of the rounded or non-rounded calculation results in overflow or saturation.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

EXTRV.W:
   temp64..0 = _shiftShortAccRightArithmetic( ac, GPR[rs]4..0 )
   if (( temp64..32 != 0 ) and ( temp64..32 != 0x1FFFFFFFF )) then
      DSPControlouflag:23 = 1
   endif
   GPR[rt]63..0 = (temp32)32 || temp32..1
   temp64..0 = temp + 1
   if (( temp64..32 != 0 ) and ( temp64..32 != 0x1FFFFFFFF )) then
      DSPControlouflag:23 = 1
   endif
EXTRV_R.W:
   temp64..0 = _shiftShortAccRightArithmetic( ac, GPR[rs]4..0 )
   if (( temp64..32 != 0 ) and ( temp64..32 != 0x1FFFFFFFF )) then
      DSPControlouflag:23 = 1
   endif
   temp64..0 = temp + 1
   if (( temp64..32 != 0 ) and ( temp64..32 != 0x1FFFFFFFF )) then
      DSPControlouflag:23 = 1
   endif
   GPR[rt]63..0 = (temp32)32 || temp32..1
EXTRV_RS.W:
   temp64..0 = _shiftShortAccRightArithmetic( ac, GPR[rs]4..0 )
   if (( temp64..32 != 0 ) and ( temp64..32 != 0x1FFFFFFFF )) then
      DSPControlouflag:23 = 1
   endif
   temp64..0 = temp + 1
   if (( temp64..32 != 0 ) and ( temp64..32 != 0x1FFFFFFFF )) then
      if ( temp64 = 0 ) then
          temp32..1 = 0x7FFFFFFF
      else
          temp32..1 = 0x80000000
      endif
      DSPControlouflag:23 = 1
   endif
   GPR[rt]63..0 = (temp32)32 || temp32..1

Exceptions:

Reserved Instruction, DSP Disabled